R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 178

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Interrupt Controller (INTC)
Notes: m1 to m4 are the number of states needed for the following memory accesses.
Rev. 2.00 Sep. 07, 2007 Page 150 of 1164
REJ09B0321-0200
Item
Interrupt
response
time
m1: Vector address read (longword read)
m2: SR save (longword write)
m3: PC save (longword write)
m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the
1. In the case of m1 = m2 = m3 = m4 = 1 Icyc.
2. In the case of Iφ:Bφ:Pφ = 120:60:30 [MHz].
No
register
banking
Register
banking
without
register
bank
overflow
Register
banking
with
register
bank
overflow
stack.
Min.
Max. 6 Icyc +
Min.
Max. 
Min.
Max. 
NMI
5 Icyc +
2 Bcyc +
1 Pcyc +
m1 + m2
2 Bcyc +
1 Pcyc +
2 (m1 + m2)
+ m3


User Break H-UDI
6 Icyc +
m1 + m2
7 Icyc +
2 (m1 + m2)
+ m3




Number of States
5 Icyc +
1 Pcyc +
m1 + m2
6 Icyc +
1 Pcyc +
2 (m1 + m2)
+ m3
5 Icyc +
1 Pcyc +
m1 + m2
14 Icyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Pcyc +
m1 + m2 +
19 (m4)
IRQ, PINT
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
3 Bcyc +
1 Pcyc +
2 (m1 + m2)
+ m3
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
14 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2 +
19 (m4)
Peripheral
Module
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
1 Bcyc +
1 Pcyc +
2 (m1 + m2)
+ m3
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
14 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2 +
19 (m4)
Remarks
120-MHz operation*
0.067 to 0.142 µs
120-MHz operation*
0.100 to 0.175 µs
120-MHz operation*
0.092 to 0.142 µs
120-MHz operation*
0.167 to 0.217 µs
120-MHz operation*
0.092 to 0.142 µs
120-MHz operation*
0.245 to 0.300 µs
1
1
1
1
1
1
*
*
*
*
*
*
2
2
2
2
2
2
:
:
:
:
:
: