R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 274

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
(b) 16-Bit Bus Channel
If a 16-bit bus is selected by the external bus width select bits in the CSn control register, A27 to
A1 are enabled as address signals for word units and A0 is disabled (fixed low level). Table 9.8
shows the data alignment corresponding to byte addresses for different data sizes.
Pins WR1 and WR0 are enabled when byte strobe mode (WRMOD = 0) is selected. Pins WR3
and WR2 are disabled. Pins BC3 to BC0 are not used.
Only the WR1 pin is enabled when one-write strobe mode (WRMOD = 1) is selected. A low-level
signal is output from the WR1 pin during write access, regardless of the data size. At this time the
WR0 pin is disabled (fixed high level). The valid byte positions are indicated by pins BC1 and
BC0.
Table 9.8
Note: The valid bits in the data bus for each data size are indicated by circles (O).
Rev. 2.00 Sep. 07, 2007 Page 246 of 1164
REJ09B0321-0200
Data Size
Byte
Word
Longword
Crosses (×) indicate bus data bits that are undefined.
Asterisks (*) indicate write/byte control bits that are disabled (fixed high level).
Data Alignment (16-Bit Bus Channel)
Byte Address
(Lower 2 Bits) [31:24] [23:16] [15:8] [7:0]
0
1
2
3
0
2
0 (1st)
2 (2nd)
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
DATA
O
×
O
×
O
O
O
O
×
O
×
O
O
O
O
O
[3]
*
*
*
*
*
*
*
*
[2]
*
*
*
*
*
*
*
*
WR/BC
L
H
L
H
L
L
L
L
[1]
[0]
H
L
H
L
L
L
L
L