R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 349

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
29, 28
27, 26
25, 24
Bit Name
MDSEL
[1:0]

DSEL[1:0]
Initial
Value
00
All 0
00
R/W
R/W
R
R/W
Description
DMA Transfer Mode Selection
These bits are used to specify the DMA transfer mode.
Setting these bits to "00" selects cycle-stealing transfer
mode.
Setting these bits to "01" selects pipelined transfer
mode.
Do not set these bits to "10" or "11". Operation is not
guaranteed if these settings are made. For details, see
section 11.4.1, DMA Transfer Mode.
00: Cycle-stealing transfer
01: Pipelined transfer
10: Setting prohibited
11: Setting prohibited
Note:
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA Transfer Condition Selection
These bits are used to specify the conditions of DMA
transfer.
Setting these bits to "00" selects single operand
transfer.
Setting these bits to "01" selects sequential operand
transfer.
Setting these bits to "11" selects non-stop transfer. For
details, see section 11.4.2, DMA Transfer Condition.
Do not set these bits to "10". Operation is not
guaranteed if this setting is made.
00: Unit operand transfer
01: Sequential operand transfer
10: Setting prohibited
11: Non-stop transfer
Section 11 Direct Memory Access Controller (DMAC)
Pipelined transfer through a single BIU is not
possible. For details on the BIU, see section
11.1, Features.
Rev. 2.00 Sep. 07, 2007 Page 321 of 1164
REJ09B0321-0200