R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 158

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Interrupt Controller (INTC)
6.3.11
DMA transfer request enable register 1 (DREQER1) is an 8-bit readable/writable register that
enables/disables the SCIF (channels 0 to 3) DMA transfer requests, and enables/disables CPU
interrupt requests.
DMA transfer request enable register 1 is initialized by a power-on reset or in deep standby mode.
Rev. 2.00 Sep. 07, 2007 Page 130 of 1164
REJ09B0321-0200
Bit
7
6
5
4
3
2
1
0
Bit Name
SCIF 3ch TX
SCIF 3ch RX
SCIF 2ch TX
SCIF 2ch RX
SCIF 1ch TX
SCIF 1ch RX
SCIF 0ch TX
SCIF 0ch RX
DMA Transfer Request Enable Register 1 (DREQER1)
Initial value:
Initial
Value
0
0
0
0
0
0
0
0
R/W:
Bit:
3ch TX
SCIF
R/W
0
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3ch RX
SCIF
R/W
0
6
Description
DMA Transfer Request Enable Bits
These bits enable/disable DMA transfer requests, and
enable/disable CPU interrupt requests.
0: DMA transfer request disabled, CPU interrupt
1: DMA transfer request enabled, CPU interrupt request
2ch TX
SCIF
R/W
0
5
request enabled
disabled
2ch RX
SCIF
R/W
0
4
1ch TX
SCIF
R/W
0
3
1ch RX
SCIF
R/W
0
2
0ch TX
SCIF
R/W
0
1
0ch RX
SCIF
R/W
0
0