R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 657

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

14.4
14.4.1
The WDT can be used to cancel software standby mode with an interrupt such as an NMI
interrupt. The procedure is described below. (The WDT does not operate when resets are used for
canceling, so keep the RES or MRES pin low until clock oscillation settles.)
1. Before making a transition to software standby mode, always clear the TME bit in WTCSR
2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the
3. After setting the STBY bit to 1 and the DEEP bit to 0 in the standby control register (STBCR:
4. The WDT starts counting by detecting the edge change of the NMI signal.
5. When the WDT count overflows, the CPG starts supplying the clock and this LSI resumes
14.4.2
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
2. Set the type of count clock used in the CKS[2:0] bits in WTCSR and the initial value of the
3. When the frequency control register (FRQCR) is written to, this LSI stops temporarily. The
4. When the WDT count overflows, the CPG resumes supplying the clock and this LSI resumes
5. The counter stops at the value of H'00.
6. Before changing WTCNT after execution of the frequency change instruction, always confirm
to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated
when the count overflows.
counter in WTCNT. These values should ensure that the time till count overflow is longer than
the clock oscillation settling time.
see section 25, Power-Down Modes), the execution of a SLEEP instruction places the system
in software standby mode and clock operation then stops.
operation. The WOVF flag in WRCSR is not set when this happens.
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
counter in WTCNT. These values should ensure that the time till count overflow is longer than
the clock oscillation settling time. Note that, the WDT counts up by the clock to be set.
WDT starts counting.
operation. The WOVF flag in WRCSR is not set when this happens.
that the value of WTCNT is H'00 by reading from WTCNT.
WDT Usage
Canceling Software Standby Mode
Changing the Frequency
Rev. 2.00 Sep. 07, 2007 Page 629 of 1164
Section 14 Watchdog Timer (WDT)
REJ09B0321-0200