R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 87

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2.4.10
Table 2.19 Bit Manipulation Instructions
Instruction
BAND.B
BANDNOT.B #imm3,@(disp12,Rn)
BCLR.B
BCLR
BLD.B
BLD
BLDNOT.B
BOR.B
BORNOT.B
BSET.B
BSET
BST.B
BST
BXOR.B
Bit Manipulation Instructions
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
#imm3,Rn
#imm3,@(disp12,Rn)
Instruction Code
0011nnnn0iii1001
0100dddddddddddd
0011nnnn0iii1001
1100dddddddddddd
0011nnnn0iii1001
0000dddddddddddd
10000110nnnn0iii
0011nnnn0iii1001
0011dddddddddddd
10000111nnnn1iii
0011nnnn0iii1001
1011dddddddddddd
0011nnnn0iii1001
0101dddddddddddd
0011nnnn0iii1001
1101dddddddddddd
0011nnnn0iii1001
0001dddddddddddd
10000110nnnn1iii
0011nnnn0iii1001
0010dddddddddddd
10000111nnnn0iii
0011nnnn0iii1001
0110dddddddddddd
Operation
(imm of (disp + Rn)) & T → T
~(imm of (disp + Rn)) & T → T
0 → (imm of (disp + Rn))
0 → imm of Rn
(imm of (disp + Rn)) → T
imm of Rn → T
~(imm of (disp + Rn))
( imm of (disp + Rn)) | T → T
~( imm of (disp + Rn)) | T → T
1 → ( imm of (disp + Rn))
1 → imm of Rn
T → (imm of (disp + Rn))
T → imm of Rn
(imm of (disp + Rn)) ^ T → T
→ T
Rev. 2.00 Sep. 07, 2007 Page 59 of 1164
Execu-
tion
Cycles
3
3
3
1
3
1
3
3
3
3
1
3
1
3
T Bit
Operation
result
Ope-ration
result


Operation
result
Operation
result
Operation
result
Operation
result
Operation
result




Operation
result
REJ09B0321-0200
SH2,
SH2E
Section 2 CPU
Compatibility
SH4 SH-2A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes