R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 347

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note: Only write to this register when the corresponding channel is not engaged in single operand
Bit
1, 0
transfer (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is
"0") and DMA transfer is disabled (DMST in the DMA activation control register (DMSCNT)
or DEN in DMA control register B for the channel (DMCNTBn) is set to "0"). Operation is not
guaranteed if this register is written to when both conditions are not satisfied.
When SACT and DACT are set to 1, output of a low DACT signal from the cycle following a
DMAC read or write cycle is enabled.
Bit Name
DTCM[1:0]
Initial
Value
Undefined R/W
R/W
Description
DMA End Signal Output Control
These bits are used to control the output of the DMA
end signal (DTEND) when the DMA transfer end
condition is detected.
When the bits are set to "00", DTEND signals on
completion of DMA transfer are disabled and the
DTEND line is fixed high.
When these bits are set to "10", the DTEND signal
goes low (is active) in the cycle after the read cycle
immediately preceding completion of DMA transfer.
When these bits are set to "10", the DTEND signal is
active in the cycle after the write cycle immediately
preceding completion of DMA transfer.
When these bits are set to "11", the DTEND signal is
active for the period of one clock cycle at the same
time as the DMA transfer end interrupt (for details, see
figure 11.9.)
However, while output of the DTEND signal is enabled
when the DMA request source selection bits (DCTG)
are set for software triggering, a valid DTEND signal
cannot be output when the requesting source is an on-
chip peripheral circuit (DCTG), regardless of the
setting of the DTEND bits.
00: Stops output of the DTEND signal
01: The DTEND signal is output on the last read cycle
10: The DTEND signal is output on the last write cycle
11: The DTEND signal is output after DMA has been
completed
Section 11 Direct Memory Access Controller (DMAC)
Rev. 2.00 Sep. 07, 2007 Page 319 of 1164
REJ09B0321-0200