R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 444
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 444 of 1196
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Rev. 2.00 Sep. 07, 2007 Page 416 of 1164
REJ09B0321-0200
Bit
2
1
Bit Name
TGFC
TGFB
Initial
Value
0
0
R/W
R/(W)*
R/(W)*
1
1
Description
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0, 3, and 4.
Only 0 can be written, for flag clearing. In channels 1
and 2, bit 2 is reserved. It is always read as 0 and the
write value should always be 0.
[Setting conditions]
•
•
[Clearing condition]
•
Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB input
capture or compare match. Only 0 can be written, for
flag clearing.
[Setting conditions]
•
•
[Clearing condition]
•
When TCNT = TGRC and TGRC is functioning as
output compare register
When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input
capture register
When 0 is written to TGFC after reading
TGFC = 1*
When TCNT = TGRB and TGRB is functioning as
output compare register
When TCNT value is transferred to TGRB by input
capture signal and TGRB is functioning as input
capture register
When 0 is written to TGFB after reading
TGFB = 1*
2
2
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