R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 827

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(1)
Reception Using DMA Controller
Note: * If the SSI encounters an error interrupt underflow/overflow,
Yes
go back to the start in the flowchart again.
No
Wait for interrupt from DMAC or SSI
Figure 18.22 Reception Using DMA Controller
define SSICR configuration bits.
from SSI module to memory.
More data to be send?
disable error interrupts,
enable error interrupts.
Setup DMA controller
Wait for idle interrupt
Disable SSI module,
Release from reset,
Enable SSI module,
enable Idle interrupt.
SSI error interrupt?
from SSI module.
End of Rx data?
to transfer data
disable DMA,
enable DMA,
DMAC:
End*
Start
Yes
No
No
Yes
Rev. 2.00 Sep. 07, 2007 Page 799 of 1164
Define TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL.
EN = 1,
DMEN = 1,
UIEN = 1, OIEN = 1
EN = 0,
DMEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Section 18 Serial Sound Interface (SSI)
REJ09B0321-0200