R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 1051

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

27.3
In this mode, all the modules connected to this LSI's internal or external bus can be read and
written to (except cache and H-UDI), allowing RAM monitoring and tuning to be carried out.
27.3.1
The AUD-II latches the AUDATA input when AUDSYNC is asserted. The following AUDATA
input format should be used.
0000
RAM Monitor Mode
Communication Protocol
Command
DIR
Spare bits (4 bits): B'0000
A3 to A0
Figure 27.1 AUDATA Input Format
Address
A31 to A28
Fixed at 1 0: Read
Bit 3
Section 27 Advanced User Debugger II (AUD-II)
Rev. 2.00 Sep. 07, 2007 Page 1023 of 1164
1: Write
D3 to D0
Bit 2
Data (in case of write only)
B write: n = 7
W write: n = 15
L write: n = 31
00: Byte
01: Word
10: Longword
Bit 1
Bit 0
REJ09B0321-0200
Dn to Dn-3