R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 323

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

10.2
The bus monitor function detects two types of bus error: illegal address access and bus timeout.
Bus error detection is performed in one bus access.
Even when data is transferred in multiple bus accesses such as burst transfer, a bus error can be
detected in one bus access.
10.2.1
When a bus error is detected, the status is saved in the bus monitor status register 1 (SYCBESTS1)
and bus monitor status register 2 (SYCBESTS2) and the CPU is notified of the bus error is
notified to the CPU.
(1)
When a bus error occurs, the status at the time (what type of error occurred and which bus was
being accessed by which bus master) is saved in the bus monitor status register 1 (SYCBESTS1)
or bus monitor status register 2 (SYCBESTS2).
Even if another bus error occurs after this, the value in the bus monitor status register
(SYCBESTS) or bus monitor status register 2 (SYCBESTS2) is not updated. When multiple bus
errors occur at the same time, multiple status bits may be set.
The bus monitor status register 1 (SYCBESTS1) or bus monitor status register 2 (SYCBESTS2)
can be cleared by writing 1 to the status clear bit (STSCLR) in the bus monitor enable register
(SYCBEEN) from the bus master. After being cleared, the status of a bus error, if generated, is
saved in the bus monitor status register 1 (SYCBESTS1) or bus monitor status register 2
(SYCBESTS2) again.
When a clear operation and a bus error happen at the same time, the clear operation has priority
and the bus error is ignored.
Saving Status in Bus Monitor Status Register or Bus Monitor Status Register 2
Bus Monitor Function
Operation when a Bus Error is Detected
Rev. 2.00 Sep. 07, 2007 Page 295 of 1164
Section 10 Bus Monitor
REJ09B0321-0200