R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 277

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 9.10 SDRAMC Commands
[Legend]
H: High level, L: Low level, V: Valid, X: Don't care
(3)
Rewriting of SDRAMC registers should only be performed when all of the conditions listed in
table 9.11 are satisfied.
Table 9.11 Register Rewrite Conditions
DSL
ACT
RD
WR
PRA
RFA
MRS
EMRS
RFS
RFX
DPD
DPDX
Function/Operation
Self-refresh
Auto-refresh
Initialization sequence
SDRAMC Register Setting Conditions
Command
Deselect
Initialize row and bank
Read
Write
Precharge all banks
Auto-refresh
Mode register set
Extended mode
register set
Self-refresh entry
Self-refresh exit
Deep-power-down
Deep-power-down exit
Register
SDRFCNT0
SDRFCNT1
SDIR0
SDIR1
SDCS
H
L
L
L
L
L
L
L
L
H
L
X
SDRAS SDCAS SDWE
L
H
L
L
L
L
X
H
X
H
L
X
Conditions
•
•
•
•
•
•
•
•
SDRAM access disabled (set in SDRAMCm*
Auto-refresh enabled (DRFEN = 1)
Power-down disabled (DPWD/DPWDCI = 0)
Deep-power-down disabled (DDPD/DDPDCI = 0)
Self-refresh disabled (DSFEN/DSFENCI = 0)
Power-down disabled (DPWD/DPWDCI = 0)
Before start of initialization sequence
After reset or after recovery from deep-power-
down
X
H
L
L
H
L
L
L
L
X
H
X
Rev. 2.00 Sep. 07, 2007 Page 249 of 1164
X
H
H
L
L
H
L
L
H
X
L
X
Section 9 Bus State Controller (BSC)
H
H → L
L → H
SDCKE BA1
X
H
H
H
H
H
H
H → L
L → H
REJ09B0321-0200
X
V
V
V
X
X
L
H
X
X
X
X
BA0
X
V
V
V
X
X
L
L
X
X
X
X
1
)