R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 367

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Note: Bits 31 to 24 correspond to channels 0 to 7, respectively (31: channel 0, 30: channel
Bit
31 to 24 DEDET
23 to 0
1, …, 24: channel 7).
Bit Name

Initial
Value
All 0
All 0
R/W
R/W
R
Description
Values read: DMA Transfer End Condition Detection
Values written: DMA Transfer End Condition
These bits are used to verify the status of DMA
transfer end condition detection for each channel.
Reading this register does not automatically clear the
bits. Once a bit has been set to "1", the value is
retained in the register as long as the bit is not cleared
by software or a reset.
•
•
When the DMA transfer end interrupt is in use and an
interrupt request generated for a given channel starts
to be handled, write a "1" to the corresponding DMA
transfer end condition detection (DEDET) bit.
When the DMA transfer end condition detection
(DEDET) bits are cleared to "0", the DMA interrupt
request status bit (DISTS) is also cleared.
Values read:
0: DMA transfer end condition not detected
1: DMA transfer end condition detected
Values written:
0: Invalid
1: Clears DMA transfer end condition detection and
Reserved
These bits are always read as 0. The write value
should always be 0.
DMA interrupt request status
Condition for setting to "1"
When the DMA transfer end condition is detected,
these bits are set to "1".
Condition for clearing to "0"
These bits are cleared to "0" by writing a "1" to the
bits to be cleared. Write "0" to bits that are not to
be cleared. While a bit is clear, it cannot be set to
"1" by a write operation.
Section 11 Direct Memory Access Controller (DMAC)
Detection, DMA Interrupt Request
Status Clear
Rev. 2.00 Sep. 07, 2007 Page 339 of 1164
REJ09B0321-0200