R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 739

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Read receive data in SCFRDR
and ORER flag in SCLSR, to 0
Clear DR, ER, BRK flags
Overrun error handling
Receive error handling
Break handling
Error handling
ORER = 1?
Figure 16.7 Sample Flowchart for Receiving Serial Data (cont)
in SCFSR,
BRK = 1?
DR = 1?
ER = 1?
End
Yes
Yes
Yes
Yes
No
No
No
No
Section 16 Serial Communication Interface with FIFO (SCIF)
• Whether a framing error or parity error has occurred in
• When a break signal is received, receive data is not
the receive data that is to be read from the receive
FIFO data register (SCFRDR) can be ascertained
from the FER and PER bits in the serial status register
(SCFSR).
transferred to SCFRDR while the BRK flag is set.
However, note that the last data in SCFRDR is H'00,
and the break data in which a framing error occurred
is stored.
Rev. 2.00 Sep. 07, 2007 Page 711 of 1164
REJ09B0321-0200