R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 446

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
• TSR2_0
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Rev. 2.00 Sep. 07, 2007 Page 418 of 1164
REJ09B0321-0200
Bit
7, 6
5 to 2
1
0
2. When writing to the timer status register (TSR), write 0 to the bit to be cleared after
Bit Name
—
—
TGFF
TGFE
reading 1. Write 1 to other bits. But 1 is not actually written and the previous value is
held.
Note:
1.
Initial value:
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Value
All 1
All 0
0
0
R/W:
Bit:
—
7
1
R
R/W
R
R
R/(W)*
R/(W)*
—
6
1
R
1
1
—
5
0
R
Description
Reserved
These bits are always read as 1. The write value
should always be 1.
Reserved
These bits are always read as 0. The write value
should always be 0.
Compare Match Flag F
Status flag that indicates the occurrence of compare
match between TCNT_0 and TGRF_0.
[Setting condition]
•
[Clearing condition]
•
Compare Match Flag E
Status flag that indicates the occurrence of compare
match between TCNT_0 and TGRE_0.
[Setting condition]
•
[Clearing condition]
•
When TCNT_0 = TGRF_0 and TGRF_0 is
functioning as compare register
When 0 is written to TGFF after reading
TGFF = 1*
When TCNT_0 = TGRE_0 and TGRE_0 is
functioning as compare register
When 0 is written to TGFE after reading
TGFE = 1*
—
4
0
R
—
3
0
R
2
2
—
2
0
R
R/(W)* R/(W)*
TGFF TGFE
1
0
1
0
0
1