R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 805

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

18.3.2
SSISR consists of status flags indicating the operational status of the SSI module and bits
indicating the current channel numbers and word numbers.
SSISR is initialized to H'02000003 by a power-on reset or in deep standby mode.
Bit
3
2
1
0
Initial value:
Initial value:
Notes: 1. This bit can be read from or written to. Writing 0 initializes the bit, but writing 1 is ignored.
R/W:
R/W:
2. The SSI clock must be kept supplied until the SSI is in the idle state.
Bit:
Bit:
Status Register (SSISR)
Bit Name
MUEN

TRMD
EN
31
—
15
—
—
R
R
0
30
—
14
—
—
R
R
0
29
—
13
—
—
R
R
0
Initial
Value
0
0
0
0
DMRQ UIRQ OIRQ IIRQ DIRQ
28
12
—
—
R
R
0
R/W*
27
11
—
—
R/W
R/W
R
R/W
R/W
R
0
1
R/W*
26
10
—
—
R
0
Description
Mute Enable
0: Module is not muted.
1: Module is muted.
Reserved
The read value is undefined. The write value should
always be 0.
Transmit/Receive Mode Select
0: Module is in receive mode.
1: Module is in transmit mode.
SSI Module Enable
0: Module is disabled.
1: Module is enabled.
1
25
—
—
1*
R
R
9
2
24
—
—
R
R
0
8
23
—
—
—
—
R
R
7
Rev. 2.00 Sep. 07, 2007 Page 777 of 1164
22
—
—
—
—
R
R
6
Section 18 Serial Sound Interface (SSI)
21
—
—
—
—
R
R
5
20
—
—
—
—
R
R
4
CHNO[1:0] SWNO IDST
19
—
—
R
R
3
0
REJ09B0321-0200
18
—
—
R
R
2
0
17
—
—
R
R
1
1
16
—
—
R
1*
R
0
2