R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 340

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
11.3.5
DMRDADR is a register used to set an address for reloading to the DMA current destination
address register (DMCDADRn).
To enable reloading, set the DMA destination address reload function enable bit (DRLOD) in
DMA control register A (DMCNTAn) to 1. In this case, set both the DMA current destination
address register (DMCDADRn) and DMA reload destination address register (DMRDADRn).
Note: Set this register so that DMA transfer is performed within the correctly aligned address
Rev. 2.00 Sep. 07, 2007 Page 312 of 1164
REJ09B0321-0200
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
boundaries for the transfer sizes listed below.
Bit:
Bit:
•
•
DMA Reload Destination Address Register (DMRDADR)
Bit Name
RDA
R/W
R/W
When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0".
When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
31
15
—
—
R/W
R/W
30
14
—
—
R/W
R/W
29
13
—
—
Initial
Value
Undefined R/W
R/W
R/W
28
12
—
—
R/W
R/W
27
11
—
—
R/W
R/W
R/W
26
10
—
—
Description
Holds destination address bits A31 to A0 for reloading
R/W
R/W
25
—
—
9
R/W
R/W
24
—
—
8
RDA
RDA
R/W
R/W
23
—
—
7
R/W
R/W
22
—
—
6
R/W
R/W
21
—
—
5
R/W
R/W
20
—
—
4
R/W
R/W
19
—
—
3
R/W
R/W
18
—
—
2
R/W
R/W
17
—
—
1
R/W
R/W
16
—
—
0