R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 116

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 4 Clock Pulse Generator (CPG)
4.5.2
Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is
not.
1. In the initial state, IFC[2:0] = B'000 and PFC[2:0] = B'011.
2. Set the desired value in the IFC[2:0] and PFC[2:0] bits. The values that can be set are limited
3. After the register bits (IFC[2:0] and PFC[2:0]) have been set, the clock is supplied of the new
Note: When executing the SLEEP instruction after the frequency has been changed, be sure to
4.6
4.6.1
Figure 4.2 is an example of connecting the external clock input. When putting the XTAL pin in
open state, make sure the parasitic capacitance is less than or equal to 10 pF. To stably input the
external clock with enough PLL stabilizing time at power on or releasing the standby, wait longer
than the oscillation stabilizing time.
For details on input conditions of the external clock, see section 29.3.1, Clock Timing.
Rev. 2.00 Sep. 07, 2007 Page 88 of 1164
REJ09B0321-0200
by the clock operating mode and the multiplication rate of PLL circuit 1. Note that if the wrong
value is set, this LSI will malfunction.
division ratio.
read the frequency control register (FRQCR) three times before executing the SLEEP
instruction.
Changing the Division Ratio
Notes on Board Design
Note on Inputting External Clock
Figure 4.2 Example of Connecting External Clock
EXTAL
XTAL
Example of connection with XTAL pin open
Open state
External clock input

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