R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 428

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.21 TIORL_0 (Channel 0)
[Legend]
X:
Notes: 1. After power-on reset, 0 is output until TIOR is set.
Rev. 2.00 Sep. 07, 2007 Page 400 of 1164
REJ09B0321-0200
Bit 3
IOC3
0
1
Don't care
2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
Bit 2
IOC2
0
1
0
1
setting is invalid and input capture/output compare is not generated.
Bit 1
IOC1
0
1
0
1
0
1
X
Bit 0
IOC0
0
1
0
1
0
1
0
1
0
1
X
X
TGRC_0
Function
Output
compare
register*
Input capture
register*
2
2
TIOC0C Pin Function
Output retained*
Initial output is 0
0 output at compare match
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
Output retained
Initial output is 1
0 output at compare match
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Description
1