R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 164

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Interrupt Controller (INTC)
As every source is assigned a different interrupt vector, the source does not need to be identified in
the exception service routine. A priority level in a range from 0 to 15 can be set for each module
by interrupt priority registers 05 to 16 (IPR05 to IPR16). The on-chip peripheral module interrupt
exception handling sets the I3 to I0 bits in SR to the priority level of the accepted on-chip
peripheral module interrupt.
6.5
Interrupt Exception Handling Vector Table and Priority
Table 6.4 lists interrupt sources and their vector numbers, vector table address offsets, and
interrupt priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from the vector numbers and vector table address offsets. In
interrupt exception handling, the exception service routine start address is fetched from the vector
table indicated by the vector table address. For details of calculation of the vector table address,
see table 5.4, Calculating Exception Handling Vector Table Addresses, in section 5, Exception
Handling.
The priorities of IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be
set freely between 0 and 15 for each pin or module by setting interrupt priority registers 01, 02,
and 05 to 16 (IPR01, IPR02, and IPR05 to IPR16). However, if two or more interrupts specified
by the same IPR among IPR05 to IPR16 occur, the priorities are defined as shown in the IPR
setting unit internal priority of table 6.4, and the priorities cannot be changed. A power-on reset
assigns priority level 0 to IRQ interrupts, PINT interrupts, and on-chip peripheral module
interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts
from those sources occur simultaneously, they are processed by the default priorities indicated in
table 6.4.
Rev. 2.00 Sep. 07, 2007 Page 136 of 1164
REJ09B0321-0200