R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 193

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

7.3.2
BAMR is a 32-bit readable/writable register. BAMR specifies bits masked in the break address
bits specified by BAR. BAMR is initialized to H'00000000 by a power-on reset or in deep
standby, but retains its previous value by a manual reset or in software standby mode or sleep
mode.
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Break Address Mask Register (BAMR)
BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24 BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16
BAM15 BAM14 BAM13 BAM12 BAM11 BAM10 BAM9 BAM8 BAM7 BAM6 BAM5 BAM4 BAM3 BAM2 BAM1 BAM0
Bit Name
BAM31 to
BAM0
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
26
10
0
0
Description
Break Address Mask
Specify bits masked in the break address bits specified
by BAR (BA31 to BA0).
0: Break address bit BAn is included in the break
1: Break address bit BAn is masked and not included
Note: n = 31 to 0
R/W
R/W
25
0
9
0
condition
in the break condition
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
Rev. 2.00 Sep. 07, 2007 Page 165 of 1164
R/W
R/W
22
0
6
0
Section 7 User Break Controller (UBC)
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
REJ09B0321-0200
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0