R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 328

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Bus Monitor
(2)
Table 10.6 shows the DMAC transfer modes and the types of bus error that may be generated by
accesses from the DMAC.
Table 10.6 DMAC Transfer Modes and Types of Bus Error Generated
[Legend]
O:
:
Note:
10.3
10.3.1
Table 10.7 describes the operations when bus error notification to the CPU is disabled with the bus
error detection enabled (by the setting of the bus monitor enable register (SYCBEEN)).
Table 10.7 Operation When the Master is Not Notified of a Bus Error
Rev. 2.00 Sep. 07, 2007 Page 300 of 1164
REJ09B0321-0200
DMAC Transfer Mode
Illegal address access*
Bus timeout*
Illegal address access
Bus timeout
DMAC Transfer Modes and Operations of Each Bus
A bus error is generated.
A bus error is not generated.
*
Usage Note
Operation when the CPU is Not Notified of a Bus Error
To enable bus error detection, the bus monitor enable register (SYCBEEN) should be
set.
Illegal address access errors equal in number to the predetermined
number of transfers are generated and the access is terminated each
time.
Bus timeouts equal in number to the predetermined number of
transfers are generated and the access is terminated each time.
Cycle Steal
O
O
O
O
Pipeline