R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 51

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(2)
PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is
referenced by a subroutine return instruction (RTS).
(3)
PC indicates the address of the instruction being executed.
2.1.4
For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and
system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried
out using a register bank. The register contents are automatically saved in the bank after the CPU
accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a
RESBANK instruction in an interrupt processing routine.
This LSI has 15 banks. For details, see the SH-2A, SH2A-FPU Software Manual and section 6.8,
Register Banks.
2.1.5
Table 2.1 lists the values of the registers after a reset.
Table 2.1
Classification
General registers
Control registers
System registers
Procedure Register (PR)
Program Counter (PC)
Register Banks
Initial Values of Registers
Initial Values of Registers
Register
R0 to R14
R15 (SP)
SR
GBR, TBR
VBR
MACH, MACL, PR
PC
Undefined
H'00000000
Initial Value
Undefined
Value of the stack pointer in the vector
address table
Bits I[3:0] are 1111 (H'F), BO and CS are
0, reserved bits are 0, and other bits are
undefined
Undefined
Value of the program counter in the vector
address table
Rev. 2.00 Sep. 07, 2007 Page 23 of 1164
REJ09B0321-0200
Section 2 CPU