R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 68

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
Rev. 2.00 Sep. 07, 2007 Page 40 of 1164
REJ09B0321-0200
Classification
Logic
operations
Shift
Branch
Types
6
12
10
Operation
Code
AND
NOT
OR
TAS
TST
XOR
ROTL
ROTR
ROTCL
ROTCR
SHAD
SHAL
SHAR
SHLD
SHLL
SHLLn
SHLR
SHLRn
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
RTV/N
Bit inversion
Logical OR
Logical AND and T bit set
Conditional branch, conditional delayed branch
Conditional branch, conditional delayed branch
Unconditional delayed branch
Unconditional delayed branch
Delayed branch to subroutine procedure
Unconditional delayed branch
Return from subroutine procedure
Return from subroutine procedure with Rm →
Function
Logical AND
Memory test and bit set
Exclusive OR
One-bit left rotation
One-bit right rotation
One-bit left rotation with T bit
One-bit right rotation with T bit
Dynamic arithmetic shift
One-bit arithmetic left shift
One-bit arithmetic right shift
Dynamic logical shift
One-bit logical left shift
n-bit logical left shift
One-bit logical right shift
n-bit logical right shift
(branch when T = 0)
(branch when T = 1)
Delayed branch to subroutine procedure
Branch to subroutine procedure
Delayed branch to subroutine procedure
Delayed return from subroutine procedure
R0 transfer
No. of
Instructions
14
16
15