R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 181

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

IRQ
RESBANK instruction
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
[Legend]
m1:
m2:
m3:
m4:
Figure 6.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in
interrupt service routine
[Legend]
m1:
m2:
m3:
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Restoration of banked registers
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Figure 6.8 Example of Pipeline Operation when IRQ Interrupt is Accepted
Instruction Execution (Register Banking with Register Bank Overflow)
2 Icyc + 3 Bcyc + 1 Pcyc
(Register Banking with Register Bank Overflow)
2 Icyc + 3 Bcyc + 1 Pcyc
F
D
Interrupt acceptance
E
2 Icyc + 17(m4)
F
M
D
M
3 Icyc
M
3 Icyc + m1 + m2
E
Interrupt acceptance
...
Rev. 2.00 Sep. 07, 2007 Page 153 of 1164
E
M
m1
1 Icyc + m1 + m2 + 2(m4)
Section 6 Interrupt Controller (INTC)
M
m4 m4
M
D
m2
M
E
M
W
E
m3
M
F
m1 m2 m3
M
...
...
REJ09B0321-0200
M
M
M
...
F
...
...
D
D