R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 904

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 20 A/D Converter (ADC)
20.3.2
ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter,
and enables or disables starting of A/D conversion by external trigger input.
ADCSR is initialized to H'0040 by a power-on reset as well as in deep standby mode, software
standby mode or module standby mode.
Rev. 2.00 Sep. 07, 2007 Page 876 of 1164
REJ09B0321-0200
Initial value:
Bit
15
14
Note:
R/W:
Bit:
*
A/D Control/Status Register (ADCSR)
Only 0 can be written to clear the flag after 1 is read.
Bit Name
ADF
ADIE
R/(W)* R/W
ADF ADIE ADST
15
0
14
0
R/W
13
0
Initial
Value
0
0
12
—
R
0
R/W
11
R/W
R/(W)*
R/W
0
R/W
TRGS[3:0]
10
0
1
Description
A/D End Flag
Status flag indicating the end of A/D conversion.
[Clearing conditions]
•
•
[Setting conditions]
•
•
•
A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at
the end of A/D conversion. Set the ADIE bit while A/D
conversion is not being made.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
R/W
9
0
Cleared by reading ADF while ADF = 1, then
writing 0 to ADF
Cleared when DMAC is activated by ADI interrupt
and ADDR is read
A/D conversion ends in single mode
A/D conversion ends for the selected channels in
multi mode
A/D conversion ends for the selected channels in
scan mode
R/W
8
0
R/W
7
CKS[1:0]
0
R/W
6
1
R/W
5
0
MDS[2:0]
R/W
4
0
R/W
3
0
R/W
2
0
CH[2:0]
R/W
1
0
R/W
0
0