R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 1055
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 1055 of 1196
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The address map gives information on the on-chip I/O registers and is configured as described
below.
1. Register Addresses (address order)
• Registers are described by functional module, in order of the corresponding section numbers.
• Access to reserved addresses that are not described in this register address list is prohibited.
• When addresses consist of 16 or 32 bits, the addresses of the MSBs are given when big-endian
2. Register Bits
• Bit configurations of the registers are described in the same order as the Register Addresses
• Reserved bits are indicated by - in the bit name.
• No entry in the bit-name column indicates that the whole register is allocated as a counter or
• When registers consist of 16 or 32 bits, the bits are given from the MSB side. The listing order
3. Register States in Each Operating Mode
• Register states are described in the same order as the Register Addresses (address order).
• For the initial state of each bit, refer to the description of the register in the corresponding
• The register states described are for the basic operating modes. If there is a specific reset for an
mode is selected.
(address order).
for holding data.
of bytes is based on big-endian mode.
section.
on-chip peripheral module, refer to the section on that on-chip peripheral module.
Section 28 List of Registers
Rev. 2.00 Sep. 07, 2007 Page 1027 of 1164
Section 28 List of Registers
REJ09B0321-0200
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