R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 877

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

19.5.6
The RFPR0 is a 16-bit read/conditionally-write registers. The RFPR is a register that contains the
received Remote Frame pending flags associated with the configured Receive Mailboxes. When a
CAN Remote Frame is successfully stored in a receive mailbox the corresponding bit is set in the
RFPR. The bit may be cleared by writing a '1' to the corresponding bit position. Writing a '0' has
no effect. In effect there is a bit position for all mailboxes. However, the bit may only be set if the
mailbox is configured by its MBC (Mailbox Configuration) to receive Remote Frames. When a
RFPR bit is set, it also sets IRR2 (Remote Frame Request Interrupt Flag) if its MBIMR (Mailbox
Interrupt Mask Register) is not set, and the interrupt signal is generated if IMR2 is not set. Please
note that these bits are only set by receiving Remote Frames and not by receiving Data frames.
• RFPR0
Note: * Only when writing a '1' to clear.
Bit 15 to 0 — Remote Request pending flags for mailboxes 15 to 0 respectively.
Bit[15:0]: RFPR0
0
1
Initial value:
R/W:
Bit:
Remote Frame Receive Pending Register 0 (RFPR0)
R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
15
0
14
0
Description
[Clearing Condition] Writing '1' (Initial value)
Corresponding Mailbox received Remote Frame
[Setting Condition] Completion of remote frame receive in corresponding
mailbox
13
0
12
0
11
0
10
0
9
0
RFPR0[15:0]
8
0
Section 19 Controller Area Network (RCAN-ET)
7
0
Rev. 2.00 Sep. 07, 2007 Page 849 of 1164
6
0
5
0
4
0
3
0
REJ09B0321-0200
2
0
1
0
0
0