R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 835
![no-image](/images/no-image-200.jpg)
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 835 of 1196
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19.2
19.2.1
The RCAN-ET device offers a flexible and sophisticated way to organise and control CAN
frames, providing the compliance to CAN2.0B Active and ISO-11898-1. The module is formed
from 5 different functional entities. These are the Micro Processor Interface (MPI), Mailbox,
Mailbox Control and CAN Interface. The figure below shows the block diagram of the RCAN-ET
Module. The bus interface timing is designed according to the peripheral bus I/F required for each
product.
peripheral bus
16-bit
Architecture
Block Diagram
CAN Interface
MCR
GSR
BCR
Micro Processor
Interface
(MPI)
Figure 19.1 RCAN-ET Architecture
IRR
IMR
REC
Transmit Buffer
CRx
Can Core
Receive Buffer
Section 19 Controller Area Network (RCAN-ET)
CTx
Rev. 2.00 Sep. 07, 2007 Page 807 of 1164
Mailbox0
Mailbox1
Mailbox2
Mailbox3
Mailbox4
Mailbox5
Mailbox6
Mailbox7
Mailbox 0 to 15 (RAM)
Mailbox0
Mailbox1
Mailbox2
Mailbox3
Mailbox4
Mailbox5
Mailbox6
Mailbox7
Mailbox 0 to 15 (register)
MBIMR
TXCR
RXPR
TXPR
TEC
Control
Signals
Mailbox Control
Mailbox8
Mailbox9
Mailbox10
Mailbox11
Mailbox12
Mailbox13
Mailbox14
Mailbox15
Mailbox8
Mailbox9
Mailbox10
Mailbox11
Mailbox12
Mailbox13
Mailbox14
Mailbox15
TXACK
ABACK
UMSR
RFPR
Status
Signals
REJ09B0321-0200
control0
LAFM
DATA
control1
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