R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 1053

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

AUDCK
AUDSYNC
AUDATA[3:0]
AUDCK
AUDSYNC
AUDATA[3:0]
AUDCK
AUDSYNC
AUDATA[3:0]
Figure 27.4 Example of Error Occurrence (Longword Read)
Figure 27.3 Example of Write Operation (Longword Write)
Figure 27.2 Example of Read Operation (Byte Read)
0000
0000
0000
1110
1010
1000
DIR
DIR
DIR
A3 to
Input
A3 to
A3 to
Input
A0
A0
A0
Input
Input/output changeover
Input/output changeover
A31 to
A31 to
A31 to
A28
A28
A28
D3 to
D0
Not Ready
Not Ready
0000
0000
Input/output changeover
Section 27 Advanced User Debugger II (AUD-II)
D31 to
D28
(Bus error)
Rev. 2.00 Sep. 07, 2007 Page 1025 of 1164
Ready
Ready
0101
0001
Not Ready
0000
Output
Output
Ready Ready
0001
(Bus error)
Ready
Ready Ready Ready
Output
0001
0001
0101
0001
0101
D3 to
Ready
(Bus error)
D0
REJ09B0321-0200
0001
D7 to
D4