R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 56

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
(9)
The T bit in the status register (SR) changes according to the result of the comparison. Whether a
conditional branch is taken or not taken depends upon the T bit condition (true/false). The number
of instructions that change the T bit is kept to a minimum to improve the processing speed.
Table 2.4
(10) Immediate Data
Byte immediate data is located in an instruction code. Word or longword immediate data is not
located in instruction codes but in a memory table. The memory table is accessed by an immediate
data transfer instruction (MOV) using the PC relative addressing mode with displacement.
With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for
21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a
register.
Table 2.5
Note: @(disp, PC) accesses the immediate data.
Rev. 2.00 Sep. 07, 2007 Page 28 of 1164
REJ09B0321-0200
SH-2A CPU
CMP/GE
BT
BF
ADD
CMP/EQ
BT
Classification
8-bit immediate
16-bit immediate
20-bit immediate
28-bit immediate
32-bit immediate
T Bit
R1,R0
TRGET0
TRGET1
#−1,R0
#0,R0
TRGET
T Bit
Immediate Data Accessing
SH-2A CPU
MOV
MOVI20
MOVI20
MOVI20S
OR
MOV.L
.DATA.L
Description
T bit is set when R0 ≥ R1.
The program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
T bit is not changed by ADD.
T bit is set when R0 = 0.
The program branches if R0 = 0.
#H'12,R0
#H'1234,R0
#H'12345,R0
#H'12345,R0
#H'67,R0
@(disp,PC),R0
.................
H'12345678
Example of Other CPU
MOV.B
MOV.W
MOV.L
MOV.L
MOV.L
Example of Other CPU
CMP.W
BGE
BLT
SUB.W
BEQ
#H'12,R0
#H'1234,R0
#H'12345,R0
#H'1234567,R0
#H'12345678,R0
R1,R0
TRGET0
TRGET1
#1,R0
TRGET