R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 238

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
Notes: 1. The initial value of the BSIZE bits in CS0 differs depending on the settings of pins MD1
To disable the operation for each channel, forcibly write out data tentatively stored in internal
write buffer. The procedure is as follows:
1. Execute read access to the channel whose operation is to be disabled.
2. Then, write 0 to the EXENB bit (operation disabled).
Rev. 2.00 Sep. 07, 2007 Page 210 of 1164
REJ09B0321-0200
Bit
21, 20
19 to 17 
16
15 to 0
2. The initial value of the EXENB bit in CS0 is 1.
Bit Name
BSIZE[1:0]
EXENB

and MD0.
Initial
Value
00*
All 0
0*
All 0
2
1
R/W
R/W
R
R/W
R
Description
External Bus Width Select
These bits specify the width of the data bus for the
external device of the corresponding channel of CSC.
The initial value for the data bus width for CSC channel
0 (CS0) differs depending on the settings of pins MD1
and MD0.
10: 8-bit bus
00: 16-bit bus
01: 32-bit bus
Reserved
These bits are always read as 0. The write value
should always be 0.
Operation Enable
This bit enables or disables the operation for the
corresponding channel of CSC. The initial value
corresponding to CS0 only is operation enabled
(EXENB = 1).
0: Operation disabled
1: Operation enabled
Reserved
These bits are always read as 0. The write value
should always be 0.