R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 581

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.7.8
When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register
(TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to
TGR by the buffer operation is the data before write.
Figure 12.113 shows the timing in this case.
Address
Write signal
TCNT clear
signal
Buffer transfer
signal
Buffer register
TGR
Figure 12.113 Contention between Buffer Register Write and TCNT Clear
Pφ
Contention between Buffer Register Write and TCNT Clear
N
TGR write cycle
Buffer register
T1
address
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
T2
Rev. 2.00 Sep. 07, 2007 Page 553 of 1164
M
N
Buffer register write data
REJ09B0321-0200