R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 1024

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25 Power-Down Modes
25.2.6
SYSCR1 is an 8-bit readable/writable register that enables or disables access to the on-chip RAM.
SYSCR1 is initialized to H'FF by a power-on reset or in deep standby mode but retains its
previous value by a manual reset or in software standby mode. Only byte access is valid.
When an RAME bit is set to 1, the corresponding on-chip RAM area is enabled. When an RAME
bit is cleared to 0, the corresponding on-chip RAM area cannot be accessed. In this case, an
undefined value is returned when reading data or fetching an instruction from the on-chip RAM,
and writing to the on-chip RAM is ignored. The initial value of an RAME bit is 1.
Note that when clearing the RAME bit to 0 to disable the on-chip RAM, be sure to execute an
instruction to read from or write to the same arbitrary address in each page before setting the
RAME bit. If such an instruction is not executed, the data last written to each page may not be
written to the on-chip RAM. Furthermore, an instruction to access the on-chip RAM should not be
located immediately after the instruction to write to SYSCR1. If an on-chip RAM access
instruction is set, normal access is not guaranteed.
Note: When writing to this register, see section 25.4, Usage Note.
Rev. 2.00 Sep. 07, 2007 Page 996 of 1164
REJ09B0321-0200
Bit
7 to 2
1
0
System Control Register 1 (SYSCR1)
Bit Name

RAME1
RAME0
Initial value:
Initial
Value
All 1
1
1
R/W:
Bit:

R
7
1
R/W
R
R/W
R/W

R
6
1
Description
Reserved
These bits are always read as 1. The write value
should always be 1.
RAM Enable 1 (corresponding RAM addresses:
H'FFF84000 to H'FFF87FFF)
0: On-chip RAM disabled
1: On-chip RAM enabled
RAM Enable 0 (corresponding RAM addresses:
H'FFF80000 to H'FFF83FFF)
0: On-chip RAM disabled
1: On-chip RAM enabled

R
5
1

R
4
1

R
3
1

R
2
1
RAME1 RAME0
R/W
1
1
R/W
0
1