R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 69

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Classification
System control
Floating-point
instructions
Types
14
19
Operation
Code
CLRT
CLRMAC
LDBANK
LDC
LDS
NOP
RESBANK Register restoration from register bank
RTE
SETT
SLEEP
STBANK
STC
STS
TRAPA
FABS
FADD
FCMP
FCNVDS
FCNVSD
FDIV
FLDI0
FLDI1
FLDS
FLOAT
FMAC
FMOV
FMUL
FNEG
Function
T bit clear
MAC register clear
Register restoration from specified register
bank entry
Load to control register
Load to system register
No operation
Return from exception handling
T bit set
Transition to power-down mode
Register save to specified register bank entry
Store control register data
Store system register data
Trap exception handling
Floating-point absolute value
Floating-point addition
Floating-point comparison
Conversion from double-precision to single-
precision
Conversion from single-precision to double-
precision
Floating-point division
Floating-point load immediate 0
Floating-point load immediate 1
Floating-point load into system register FPUL
Conversion from integer to floating-point
Floating-point multiply and accumulate
operation
Floating-point data transfer
Floating-point multiplication
Floating-point sign inversion
Rev. 2.00 Sep. 07, 2007 Page 41 of 1164
REJ09B0321-0200
Section 2 CPU
No. of
Instructions
36
48

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