R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 102

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R5S72011

Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Section 4 Clock Pulse Generator (CPG)
Figure 4.1 shows a block diagram of the clock pulse generator.
Rev. 2.00 Sep. 07, 2007 Page 74 of 1164
REJ09B0321-0200
[Legend]
FRQCR:
STBCR:
STBCR2:
STBCR3:
STBCR4:
STBCR5:
MD_CLK1
MD_CLK0
EXTAL
CKIO
XTAL
Frequency control register
Standby control register
Standby control register 2
Standby control register 3
Standby control register 4
Standby control register 5
oscillator
Crystal
Figure 4.1 Block Diagram of Clock Pulse Generator
Clock frequency
control circuit
FRQCR
(×1, 2, 3, 4, 6, 8)
On-chip oscillator
PLL circuit 1
PLL circuit 2
(×2, 4)
CPG control unit
STBCR
Peripheral bus
Divider
Bus interface
×1
×1/2
×1/3
×1/4
×1/6
×1/8
×1/12
STBCR2
Standby control circuit
STBCR3
Internal clock
(Iφ, Max. :
120 MHz (Regular specifications),
100 MHz (Wide-range specifications))
Bus clock
(Bφ = CKIO, Max. 60 MHz)
Peripheral clock
(Pφ, Max. 40 MHz)
STBCR4
STBCR5

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