R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 394

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
11.12
Transfer speeds are calculated as shown below.
(1)
• DMA transfer mode: cycle-stealing transfer mode/pipelined transfer mode
• Transfer unit (one data size): properly aligned 32-bit data
• Operating clock: 60 MHz
• Number of cycles for access to external devices:
(2)
• Cycle-stealing transfer mode
• Pipelined transfer mode
Note: During transfer in the pipelined transfer mode, most read and write cycles overlap.
An example of the calculation of transfer speed is given below.
(a)
Maximum speed of transfer between on-chip RAM (0 wait) and on-chip RAM (0 wait).
• Cycle-stealing transfer mode
• Pipelined transfer mode
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REJ09B0321-0200
four cycles for reading; and
two cycles for writing.
Pipelined transfer through a single BIU is not possible. See section 11.4.1 (2), Pipelined
Transfer Mode.
Conditions for Calculation
Formulae Used in Calculation
Transfer between On-chip RAM
(data size in unit data transfer) / (number of read cycles + number of write cycles +
one idle cycle) × operating clock
(data size in unit data transfer) / (whichever is larger of number of read or write cycles) ×
operating clock
4 bytes / (1 read cycle + 1 write cycle + 1 idle cycle) × 60 MHz = 79.8 Mbytes/sec
Transfer Speed