R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 125

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.2
5.2.1
Table 5.5 shows the configuration of pins relating to the resets.
Table 5.5
5.2.2
A reset is the highest-priority exception handling source. There are two kinds of resets, power-on
and manual. As shown in table 5.6, the CPU state is initialized by both a power-on reset and a
manual reset. The FPU state is initialized by a power-on reset, but not by a manual reset. On-chip
peripheral module registers except a few registers are initialized by a power-on reset, but not by a
manual reset.
Table 5.6
Pin Name
Power-on reset
Manual reset
Type
Power-on
reset
Resets
Input/Output Pins
Types of Reset
RES
Low
High
High
Conditions for Transition to Reset State
Pin Configuration
Reset States
H-UDI Command MRES
—
H-UDI reset assert
command is set
Command other
than H-UDI reset
assert is set
Symbol
RES
MRES
I/O
Input
Input
—
—
—
Function
When this pin is driven low, this LSI shifts to the power-on
reset processing
When this pin is driven low, this LSI shifts to the manual
reset processing.
WDT
Overflow
—
—
Power-on
reset
CPU
Initialized
Initialized
Initialized
Rev. 2.00 Sep. 07, 2007 Page 97 of 1164
On-Chip
Peripheral
Modules, I/O Port
Initialized *
Initialized *
Initialized *
Internal States
Section 5 Exception Handling
1
1
1
REJ09B0321-0200
WRCSR of
WDT, FRQCR
of CPG
Initialized
Initialized
Not initialized