R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 803

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
9
8
7
Bit Name
PDTA
DEL

Initial
Value
0
0
0
R/W
R/W
R/W
R
Description
•
•
•
Serial Data Delay
0: 1 clock cycle delay between SSIWS and SSIDATA
1: No delay between SSIWS and SSIDATA
Reserved
The read value is undefined. The write value should
always be 0.
DWL = 010, 011, 100, 101 (with a data word length
of 18, 20, 22 or 24 bits), PDTA = 0 (left-aligned)
The data bits used in SSIRDR or SSITDR are the
following:
Bits 31 down to (32 minus the number of bits in the
data word length specified by DWL).
That is, If DWL = 011, the data word length is 20
bits; therefore, bits 31 to 12 in either SSIRDR or
SSITDR are used. All other bits are ignored or
reserved.
DWL = 010, 011, 100, 101 (with a data word length
of 18, 20, 22 or 24 bits), PDTA = 1 (right-aligned)
The data bits used in SSIRDR or SSITDR are the
following:
Bits (the number of bits in the data word length
specified by DWL minus 1) to 0
i.e. if DWL = 011, then DWL = 20 and bits 19 to 0
are used in either SSIRDR or SSITDR. All other bits
are ignored or reserved.
DWL = 110 (with a data word length of 32 bits), the
PDTA setting is ignored.
All data bits in SSIRDR or SSITDR are used on the
audio serial bus.
Rev. 2.00 Sep. 07, 2007 Page 775 of 1164
Section 18 Serial Sound Interface (SSI)
REJ09B0321-0200