R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 26
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
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Section 25 Power-Down Modes........................................................................ 985
25.1 Features.............................................................................................................................. 985
25.2 Register Descriptions......................................................................................................... 987
25.3 Operation ......................................................................................................................... 1002
25.4 Usage Note....................................................................................................................... 1011
Section 26 User Debugging Interface (H-UDI)............................................... 1013
26.1 Features............................................................................................................................ 1013
26.2 Input/Output Pins............................................................................................................. 1014
26.3 Register Descriptions....................................................................................................... 1015
26.4 Operation ......................................................................................................................... 1017
26.5 Usage Notes ..................................................................................................................... 1020
Rev. 2.00 Sep. 07, 2007 Page xxvi of xxviii
25.1.1 Power-Down Modes ............................................................................................. 985
25.2.1 Standby Control Register (STBCR)...................................................................... 988
25.2.2 Standby Control Register 2 (STBCR2)................................................................. 989
25.2.3 Standby Control Register 3 (STBCR3)................................................................. 991
25.2.4 Standby Control Register 4 (STBCR4)................................................................. 992
25.2.5 Standby Control Register 5 (STBCR5)................................................................. 994
25.2.6 System Control Register 1 (SYSCR1) .................................................................. 996
25.2.7 System Control Register 2 (SYSCR2) .................................................................. 997
25.2.8 RAM Retaining Area Specifying Register (RAMKP).......................................... 998
25.2.9 Deep Standby Oscillation Settling Clock Select Register (DSCNT) .................... 999
25.2.10 Deep Standby Cancel Source Flag Register (DSFR).......................................... 1000
25.3.1 Sleep Mode ......................................................................................................... 1002
25.3.2 Software Standby Mode...................................................................................... 1003
25.3.3 Software Standby Mode Application Example................................................... 1005
25.3.4 Deep Standby Mode ........................................................................................... 1006
25.3.5 Module Standby Function................................................................................... 1011
25.4.1 Note on Setting Registers ................................................................................... 1011
25.4.2 Note on Canceling Standby Mode when an External Clock is being Input ........ 1011
26.3.1 Bypass Register (SDBPR) .................................................................................. 1015
26.3.2 Instruction Register (SDIR) ................................................................................ 1016
26.4.1 TAP Controller ................................................................................................... 1017
26.4.2 Reset Types......................................................................................................... 1018
26.4.3 UDTDO Output Timing...................................................................................... 1018
26.4.4 H-UDI Reset ....................................................................................................... 1019
26.4.5 H-UDI Interrupt .................................................................................................. 1019
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