R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 390

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 11 Direct Memory Access Controller (DMAC)
11.9
The number of bits (transfer data size) for a single data transfer can be selected from among the
byte (8 bits), word (16 bits), and the longword (32 bits).
Figure 11.12 is an example of DMA data-byte control for a 32-bit wide bus.
This transfer data size cannot exceed either of the data bus bit widths supported by the source and
destination for DMA transfer. The data bus widths are fixed by the hardware.
Rev. 2.00 Sep. 07, 2007 Page 362 of 1164
REJ09B0321-0200
8-bit transfer
16-bit transfer
State of
address bits
State of
address bits
Units of Transfer and Positioning of Bytes for Transfer
Figure 11.12 Example of DMA Data-Byte Control for 32-bit Bus Width
H'FF00 4000
H'FF00 4001
H'FF00 4002
H'FF00 4003
H'FF00 8002
H'FF00 8004
Source side
Source side
D0 to D31
D0 to D31
DMAC internal 32-bit data buffers
DMAC internal 32-bit data buffers
: Byte/bytes being handled
D0 to D31
D0 toD31
Destination side
Destination side
H'FF60 0806
H'FF60 0808
H'0040 0203
H'0040 0204
H'0040 0205
H'0040 0206
State of
address bits
State of
address bits