R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 799

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

18.3.1
SSICR is a readable/writable 32-bit register that controls the IRQ, selects the polarity status, and
sets operating mode.
SSICR is initialized to H'00000000 by a power-on reset or in deep standby mode.
Bit
31 to 29
28
27
26
25
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Control Register (SSICR)
SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL
Bit Name
—
DMEN
UIEN
OIEN
IIEN
R/W
31
15
—
R
0
0
R/W
30
14
—
R
0
0
R/W
29
13
—
R
0
0
Initial
Value
All 0
0
0
0
0
DMEN UIEN OIEN IIEN DIEN
R/W
R/W
28
12
0
0
R/W
R/W
27
11
R/W
R
R/W
R/W
R/W
R/W
0
0
R/W
R/W
26
10
0
0
Description
Reserved
The read value is not guaranteed. The write value
should always be 0.
DMA Enable
Enables/disables the DMA request.
0: DMA request is disabled.
1: DMA request is enabled.
Underflow Interrupt Enable
0: Underflow interrupt is disabled.
1: Underflow Interrupt is enabled.
Overflow Interrupt Enable
0: Overflow interrupt is disabled.
1: Overflow interrupt is enabled.
Idle Mode Interrupt Enable
0: Idle mode interrupt is disabled.
1: Idle mode interrupt is enabled.
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
CHNL[1:0]
23
—
R
0
7
0
Rev. 2.00 Sep. 07, 2007 Page 771 of 1164
R/W
R/W
22
0
6
0
Section 18 Serial Sound Interface (SSI)
CKDV[2:0]
R/W
R/W
21
0
5
0
DWL[2:0]
R/W
R/W
20
0
4
0
MUEN
R/W
R/W
19
0
3
0
REJ09B0321-0200
R/W
18
—
R
0
2
0
SWL[2:0]
TRMD EN
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0