R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 842

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 19 Controller Area Network (RCAN-ET)
• Mailbox-0
Note: MBC[1] of MB0 is always "1".
• Mailbox-15 to 1
NMC (New Message Control): When this bit is set to '0', the Mailbox of which the RXPR or
RFPR bit is already set does not store the new message but maintains the old one and sets the
UMSR correspondent bit. When this bit is set to '1', the Mailbox of which the RXPR or RFPR bit
is already set overwrites with the new message and sets the UMSR correspondent bit.
Important: Please note that if a remote frame is overwritten with a data frame or vice versa could
be that both RXPR and RFPR flags (together with UMSR) are set for the same Mailbox. In this
case the RTR bit within the Mailbox Control Field should be relied upon.
ATX (Automatic Transmission of Data Frame): When this bit is set to '1' and a Remote Frame
is received into the Mailbox DLC is stored. Then, a Data Frame is transmitted from the same
Mailbox using the current contents of the message data and updated DLC by setting the
corresponding TXPR automatically. The scheduling of transmission is still governed by ID
priority or Mailbox priority as configured with the Message Transmission Priority control bit
(MCR.2). In order to use this function, MBC[2:0] needs to be programmed to be B'001. When a
transmission is performed by this function, the DLC (Data Length Code) to be used is the one that
has been received. Application needs to guarantee that the DLC of the remote frame correspond to
the DLC of the data frame requested.
Important: When ATX is used and MBC = B'001 the filter for the IDE bit cannot be used since
ID of remote frame has to be exactly the same as that of data frame as the reply message.
Rev. 2.00 Sep. 07, 2007 Page 814 of 1164
REJ09B0321-0200
NMC
0
1
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
15
15
R
R
0
0
0
0
Description
Overrun mode (Initial value)
Overwrite mode
14
14
R
R
0
0
0
0
NMC
NMC
R/W
R/W
13
13
0
0
R/W
ATX DART
12
12
R
0
0
0
R/W
11
11
R
0
0
0
R/W
R/W
10
10
1
1
MBC[2:0]
MBC[2:0]
R/W
R/W
9
1
9
1
R/W
R/W
8
1
8
1
R
R
7
0
7
0
0
0
R
R
6
0
6
0
0
0
R
R
5
0
5
0
0
0
R
R
4
0
4
0
0
0
R/W
R/W
3
0
3
0
R/W
R/W
DLC[3:0]
DLC[3:0]
2
0
2
0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0