R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 265

• Manufacturer Part Number: R5S72011
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.18
When writing to the external address space or making SDRAM settings in power-on reset
exception handling or cancellation of deep standby mode, be sure to set bits ACOSW[3:0] in
ACSWR to B'0011 beforehand.
ACSWR is initialized to H'00000000 by a power-on reset and entry to deep standby mode, but is
not initialized by a manual reset, entry to sleep mode, or entry to software standby mode.
Bit
31 to 4
Bit
7 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
AC Characteristics Switching Register (ACSWR)
Bit Name
DCKSC
[7:0]
Bit Name

R/W
R/W
31
—
—
15
0
0
R/W
R/W
30
—
—
14
0
0
R/W
R/W
29
—
—
Initial
Value
H'0F
13
0
0
Initial
Value
All 0
R/W
R/W
28
—
—
12
0
0
R/W
R/W
27
—
—
11
0
0
R/W
R/W
R/W
R/W
R/W
R/W
26
—
—
10
0
0
Description
Clock Stop Control Signal Assert Cycle Count Setting
These bits specify the interval from the point at which
the deep-power-down transition command is issued
until the clock stop signal goes high level to stop the
CKIO (high level), and the interval from the point at
which the clock stop signal goes low level to start the
CKIO operation until the recover command is issued.
00000000: 0 cycle
00001111: 15 cycles
11111111: 255 cycles
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
R/W
25
—
—
0
:
:
9
0
R/W
R/W
24
—
—
0
8
0
R/W
R/W
23
—
—
0
7
0
Rev. 2.00 Sep. 07, 2007 Page 237 of 1164
R/W
R/W
22
—
—
0
6
0
Section 9 Bus State Controller (BSC)
R/W
R/W
21
—
—
0
5
0
R/W
R/W
20
—
—
0
4
0
R/W
R/W
19
—
0
3
0
ACOSW[3:0]
R/W
R/W
REJ09B0321-0200
18
—
0
2
0
R/W
R/W
17
—
0
1
0
R/W
R/W
16
—
0
0
0