R5S72011 RENESAS [Renesas Technology Corp], R5S72011 Datasheet - Page 442
R5S72011
Manufacturer Part Number
R5S72011
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72011.pdf
(1196 pages)
- Current page: 442 of 1196
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Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.3.6
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The
MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5.
• TSR_0, TSR_1, TSR_2, TSR_3, TSR_4
Rev. 2.00 Sep. 07, 2007 Page 414 of 1164
REJ09B0321-0200
Bit
7
6
5
Bit Name
TCFD
—
TCFU
Timer Status Register (TSR)
Note:
1.
Initial value:
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Value
1
1
0
R/W:
Bit:
TCFD
7
1
R
R/W
R
R
R/(W)*
—
6
1
R
1
TCFU TCFV TGFD TGFC TGFB TGFA
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Description
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1 to 4.
In channel 0, bit 7 is reserved. It is always read as 1
and the write value should always be 1.
0: TCNT counts down
1: TCNT counts up
Reserved
This bit is always read as 1. The write value should
always be 1.
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase
counting mode. Only 0 can be written, for flag clearing.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0 and the write value should always be 0.
[Setting condition]
•
[Clearing condition]
•
5
0
1
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
When 0 is written to TCFU after reading TCFU = 1*
4
0
1
3
0
1
2
0
1
1
0
1
0
0
1
2
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