MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 282

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 7 Background Debug Module (S12XBDMV2)
7.1.2
BDM is available in all operating modes but must be enabled before firmware commands are executed.
Some systems may have a control bit that allows suspending thefunction during background debug mode.
7.1.2.1
All of these operations refer to the part in run mode and not being secured. The BDM does not provide
controls to conserve power during run mode.
7.1.2.2
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run
mode operation. Secure operation prevents BDM and CPU accesses to non-volatile memory (Flash and/or
EEPROM) other than allowing erasure. For more information please see
282
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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Active out of reset in special single chip mode
Nine hardware commands using free cycles, if available, for minimal CPU intervention
Hardware commands not requiring active BDM
14 firmware commands execute from the standard BDM firmware lookup table
Software control of BDM operation during wait mode
Software selectable clocks
Global page access functionality
Enabled but not active out of reset in emulation modes (if modes available)
CLKSW bit set out of reset in emulation modes (if modes available).
When secured, hardware commands are allowed to access the register space in special single chip
mode, if the non-volatile memory erase test fail.
Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices
is 0xC1)
BDM hardware commands are operational until system stop mode is entered (all bus masters are
in stop mode)
Normal modes
General operation of the BDM is available and operates the same in all normal modes.
Special single chip mode
In special single chip mode, background operation is enabled and active out of reset. This allows
programming a system with blank memory.
Emulation modes (if modes available)
In emulation mode, background operation is enabled but not active out of reset. This allows
debugging and programming a system in this mode more easily.
Modes of Operation
Regular Run Modes
Secure Mode Operation
MC9S12XE-Family Reference Manual , Rev. 1.23
Section 7.4.1,
Freescale Semiconductor
“Security”.