MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 339

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2 data entries, thus in this case the DBGCNT[0] is incremented after each separate entry. In Detail mode
DBGCNT[0] remains cleared whilst the other DBGCNT bits are incremented on each trace buffer entry.
XGATE and CPU12X COFs occur independently of each other and the profile of COFs for the two sources
is totally different. When both sources are being traced in Normal or Loop1 mode, for each COF from one
source, there may be many COFs from the other source, depending on user code. COF events could occur
far from each other in the time domain, on consecutive cycles or simultaneously. When a COF occurs in
either source (S12X or XGATE) a trace buffer entry is made and the corresponding CDV or XDV bit is
set. The current PC of the other source is simultaneously stored to the trace buffer even if no COF has
occurred, in which case CDV/XDV remains cleared indicating the address is not associated with a COF,
but is simply a snapshot of the PC contents at the time of the COF from the other source.
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL
or XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is
always stored to trace buffer byte3 and the byte at the higher address is stored to byte2
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Other Modes
Other Modes
Other Modes
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
CPU12X
CPU12X
XGATE
XGATE
Mode
Detail
Detail
Both
CXINF1
CXINF2
CXINF1
CXINF2
XINF0
XINF1
XINF1
XINF3
CINF1
CINF3
7
CADRH1
CADRH2
CADRH1
CADRH2
CPCH1
CPCH3
6
MC9S12XE-Family Reference Manual Rev. 1.23
Table 8-43. Trace Buffer Organization
CADRM1
CADRM2
CADRM1
CADRM2
XPCM0
XPCM1
XPCM1
XPCM3
CPCM1
CPCM3
5
8-Byte Wide Word Buffer
CADRL1
CADRL2
CADRL1
CADRL2
XPCL0
XPCL1
XPCL1
XPCL3
CPCL1
CPCL3
4
CDATAH1
CDATAH2
XDATAH1
XDATAH2
CINF0
CINF1
CINF0
CINF2
XINF0
XINF2
3
Chapter 8 S12X Debug (S12XDBGV3) Module
CDATAL1
CDATAL2
XDATAL1
XDATAL2
CPCH0
CPCH1
CPCH0
CPCH2
2
XADRM1
XADRM2
XADRM1
XADRM2
CPCM0
CPCM1
CPCM0
CPCM2
XPCM0
XPCM2
1
XADRL1
XADRL2
XADRL1
XADRL2
CPCL0
CPCL1
CPCL0
CPCL2
XPCL0
XPCL2
0
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