MC9S12XEP100CAL Freescale Semiconductor, MC9S12XEP100CAL Datasheet - Page 80

• Manufacturer Part Number: MC9S12XEP100CAL
• Description: IC MCU 16BIT 1M FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEP100CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 64 KB
• Interface Type: CAN/SCI/SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 12-bit
• Package: 112LQFP
• Family Name: HCS12X
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 1.8|2.8|5 V
• For Use With: EVB9S12XEP100 - BOARD EVAL FOR MC9S12XEP100DEMO9S12XEP100 - BOARD DEMO FOR MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1 Device Overview MC9S12XE-Family
MPU is set, access to system resources is only allowed if enabled by a memory range descriptor as defined
in the Memory Protection Unit (MPU) description.
1.4.4.2
This state is intended for carrying out system tasks and is entered by setting the U bit of the condition codes
register while in Supervisor state. Restrictions apply for the execution of several CPU instructions in User
state and access to system resources is only allowed in if enabled by a memory range descriptor as defined
in the Memory Protection Unit (MPU) description.
1.5
The MCU security feature allows the protection of the on chip Flash and emulated EEPROM memory. For
a detailed description of the security features refer to the S12X9SEC description.
1.6
Consult the S12XCPU manual and the S12XINT description for information on exception processing.
1.6.1
Resets are explained in detail in the Clock Reset Generator (CRG) description.
1.6.2
Table 1-14
(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each
I-bit maskable service request is a configuration register. It selects if the service request is enabled, the
service request priority level and whether the service request is handled either by the S12X CPU or by the
XGATE module.
80
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Vector Address
Security
Resets and Interrupts
lists all interrupt sources and vectors in the default order of priority. The interrupt module
Resets
Vectors
$FFFE
$FFFE
$FFFE
$FFFE
$FFFC
User State
$FFFA
Table 1-13. Reset Sources and Vector Locations
MC9S12XE-Family Reference Manual , Rev. 1.23
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
COP watchdog reset
External pin RESET
Clock monitor reset
Reset Source
Mask
None
None
None
None
None
None
CCR
PLLCTL (CME, SCME)
COP rate select
Local Enable
None
None
None
None
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