EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 100

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–8
Table 5–7. Mapping between Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs
Arria II GX Device Handbook, Volume 1
Clock Control Block Inputs
inclk[0], inclk[1]
inclk[2]
inclk[3]
Note to
(1) The left side of the Arria II GX device only allows PLL counter outputs as the dynamic clock source selection to the GCLK network. Therefore,
inclk[0] can be fed by PLL counters C4 or C6, while inclk[1] can only be fed by PLL counter C5.
Table
5–7:
1
Figure 5–4. Arria II GX GCLK Control Block
Notes to
(1) You can only dynamically control these clock select signals through internal logic when the device is operating in user
(2) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically
(3) The left side of the Arria II GX device only allows PLL counter outputs as the dynamic clock source selection to the
(4) This is only available on the left side of the Arria II GX device.
Table 5–7
clock control block inputs.
When combining the PLL outputs and clock pins in the same clock control block,
ensure that these clock sources are implemented on the same side of the device.
For all possible legal inclk sources for each GCLK and RCLK network, refer to
Table 5–2 on page 5–5
(1)
mode.
controlled during user mode operation.
GCLK network.
Figure
Can be fed by any of the four dedicated clock pins on the same side
Can be fed by PLL counters C0 and C2 from the two corner PLLs on the same side of the
Arria II GX device
Can be fed by PLL counters C1 and C3 from the two corner PLLs on the same side of the
Arria II GX device
lists the mapping between the input clock pins, PLL counter outputs, and
5–4:
CLKSELECT[1..0]
PLL Counter
This multiplexer
supports user-controllable
dynamic switching
Outputs (3)
through
(1)
Table 5–6 on page
2
2
CLK
Pin
Description
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
2
Enable/
Disable
GCLK
CLK
5–7.
Pin
Block Clock Lines
Inter-Transceiver
Static Clock
Internal
Select (2)
Clock Networks in Arria II GX Devices
Logic
Internal
(4)
Logic
© July 2010 Altera Corporation