EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 162

• Manufacturer Part Number: EP2AGX65DF29C6N
• Description: IC ARRIA II GX FPGA 65K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX65DF29C6N

• Number Of Logic Elements/cells: 60214
• Number Of Labs/clbs: 2530
• Total Ram Bits: 5246
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 63250
• # I/os (max): 364
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 63250
• Ram Bits: 5557452.8
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–4
Table 7–1. Arria II GX DQ/DQS Bus Mode Pins
Table 7–2. Number of DQ/DQS Groups and I/O Modules in Arria II GX Devices per Side (Part 1 of 2)
Arria II GX Device Handbook, Volume 1
×4
×8/×9
×16/×18
×32/×36
Notes to
(1) This represents the maximum number of DQ pins (including parity and data mask pins) connected to the DQS bus network with single-ended
(2) The DM pin can be supported if the differential DQS is not used and the group does not have additional signals.
(3) Two ×4 DQ/DQS groups are stitched together to create a ×8/×9 group, so there are a total of 12 pins in this group.
(4) Four ×4 DQ/DQS groups are stitched together to create a ×16/×18 group.
(5) Eight ×4 DQ/DQS groups are stitched together to create a ×32/×36 group.
EP2AGX45
EP2AGX65
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
Device
DQS signaling. If you are using differential or complementary DQS signaling, the maximum number of data-per-group decreases by one. This
number may vary per DQ/DQS group in a particular device. For the DDR, DDR2, and DDR3 interface, the number of pins is further reduced for
interfaces larger than ×8 due to the need of one DQS pin for each ×8 group. Check with the pin table for the accurate number per group.
Mode
(3)
Table
(4)
(5)
f
7–1:
358-Pin Ultra
FineLine BGA
572-Pin
FineLine BGA
Package
DQSn Support
The Arria II GX device supports DQ and DQS signals with DQ bus modes of ×4,
×8/×9, ×16/×18, or ×32/×36. The DDR, DDR2, and DDR3 interfaces use one DQS pin
for each ×8 group; for example, an interface with a ×72 DDR2 DIMM needs nine DQS
pins. When any of these pins are not used for memory interfacing, you can use them
as user I/Os. In addition, you can use any DQSn or CQn pins not used for clocking as
DQ (data) pins.
DQS/CQ and DQSn/CQn pin pair.
Figure 7–3
side of the Arria II GX device. These figures represent the die-top view of the
Arria II GX device.
Table 7–2
Arria II GX device.
For more information about DQ/DQS groups pin-out restriction format, refer to the
Arria II GX Pin Connection
Yes
Yes
Yes
Yes
Top/Bottom
Right
Top/Bottom
Right
shows the number of I/O modules and DQ/DQS groups per side of the
Side
through
CQn Support
Table 7–1
Yes
Yes
Yes
No
Figure 7–9
I/O Module
Number of
(1)
3
2
4
6
lists pin support per DQ/DQS bus mode, including the
Guidelines.
Parity or DM
(Optional)
show the maximum number of DQ/DQS groups per
No
Yes
Yes
Yes
(2)
×4
12
6
4
8
Chapter 7: External Memory Interfaces in Arria II GX Devices
Data Pins per Group
Typical Number
16 or 18
32 or 36
Number of DQ/DQS Groups
8 or 9
of
×8/×9
4
3
2
4
6
Arria II GX Memory Interfaces Pin Support
© July 2010 Altera Corporation
×16/×18
Data Pins per Group
1
0
2
2
Maximum Number
11
23
47
of
5
×32/×36
0
0
0
0
(1)